-- $Id: $
-- File name:   tb_USB_RCVR.vhd
-- Created:     10/13/2010
-- Author:      Christopher Sakalis
-- Lab Section: 4
-- Version:     1.0  Initial Test Bench

library ieee;
--library gold_lib;   --UNCOMMENT if you're using a GOLD model
use ieee.std_logic_1164.all;
--use gold_lib.all;   --UNCOMMENT if you're using a GOLD model

entity tb_USB_RCVR is
--generic (Period : Time := 83.13165 ns);
--generic (Period : Time := 83.34 ns);
--generic (Period : Time := 83.54835 ns);
generic (Period : Time := 8.34 ns);
end tb_USB_RCVR;

architecture TEST of tb_USB_RCVR is

  function INT_TO_STD_LOGIC( X: INTEGER; NumBits: INTEGER )
     return STD_LOGIC_VECTOR is
    variable RES : STD_LOGIC_VECTOR(NumBits-1 downto 0);
    variable tmp : INTEGER;
  begin
    tmp := X;
    for i in 0 to NumBits-1 loop
      if (tmp mod 2)=1 then
        res(i) := '1';
      else
        res(i) := '0';
      end if;
      tmp := tmp/2;
    end loop;
    return res;
  end;

  component USB_RCVR
    PORT(
         CLK : in std_logic;
         RST_N : in std_logic;
         D_PLUS : in std_logic;
         D_MINUS : in std_logic;
         R_ENABLE : in std_logic;
         R_DATA : out std_logic_vector (7 downto 0);
         FULL : out std_logic;
         EMPTY : out std_logic;
         R_ERROR : out std_logic;
         RCVING : out std_logic
    );
  end component;

-- Insert signals Declarations here
  signal CLK : std_logic;
  signal RST_N : std_logic;
  signal D_PLUS : std_logic;
  signal D_MINUS : std_logic;
  signal R_ENABLE : std_logic;
  signal R_DATA : std_logic_vector (7 downto 0);
  signal FULL : std_logic;
  signal EMPTY : std_logic;
  signal R_ERROR : std_logic;
  signal RCVING : std_logic;

-- signal <name> : <type>;

begin

CLKGEN: process
  variable CLK_tmp: std_logic := '0';
begin
  CLK_tmp := not CLK_tmp;
  CLK <= CLK_tmp;
  wait for Period/2;
end process;

  DUT: USB_RCVR port map(
                CLK => CLK,
                RST_N => RST_N,
                D_PLUS => D_PLUS,
                D_MINUS => D_MINUS,
                R_ENABLE => R_ENABLE,
                R_DATA => R_DATA,
                FULL => FULL,
                EMPTY => EMPTY,
                R_ERROR => R_ERROR,
                RCVING => RCVING
                );

--   GOLD: <GOLD_NAME> port map(<put mappings here>);

process

  begin

-- Insert TEST BENCH Code Here

--     RST_N <= 
--     D_PLUS <= 
--     D_MINUS <= 
--     R_ENABLE <=


     RST_N <= '1';
     R_ENABLE <= '0';
     D_PLUS <= '1'; --??????????????????  
     D_MINUS <= '0'; --?????????????????? 
     wait for period;
     RST_N <= '0';
     --wait for 16*period;
     wait for 8*period;
     RST_N <= '1';
------------------------------
     wait for 8*period;
     R_ENABLE <='1';
     wait for 8*period;

     ----wait for 8*period;
     --D_PLUS <= '0'; --??????????????????  
     --D_MINUS <= '1'; --?????????????????? 
     wait for 8*period;

--????????????????????????????
--????????????????????????????
      D_PLUS <= '1';
      D_MINUS <= '0';
      wait for (8*period);
      D_PLUS <= '0';
      D_MINUS <= '1';
--$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
-------------Old TB case:
       wait for (8*period);
       D_PLUS <= '1';
       D_MINUS <= '0';
       wait for (8*period);
       D_PLUS <= '0';
       D_MINUS <= '1';
 
       wait for (8*period);
       D_PLUS <= '1';
       D_MINUS <= '0';
 
       wait for (8*period);
       D_PLUS <= '0';
       D_MINUS <= '1';
 
       wait for (8*period);
       D_PLUS <= '1';
       D_MINUS <= '0';
 
       wait for (8*period);
       D_PLUS <= '0';
       D_MINUS <= '1';
       
       wait for (8*period);
       D_PLUS <= '0';
       D_MINUS <= '1';

-------Received the SYNC BIT...OK
       --wait;
       -------------------
       wait for (8*period);
       D_PLUS <= '1';
       D_MINUS <= '0';
 
 --=====Case(iv)====================================================================================
       wait for (6*8*period);
 --=================================================================================================
 
 
       wait for (2*8*period);
       D_PLUS <= '0';
       D_MINUS <= '0';

       wait for (8*period);
       D_PLUS <= '1';
       D_MINUS <= '0';

       --Case: Successful store (goes to EIDLE) OK
       --wait;
       
------------------------------------------------       
------------------------------------------------


wait for (8*period);
D_PLUS <= '0';
D_MINUS <= '1';

wait for (8*period);
D_PLUS <= '1';
D_MINUS <= '0';

wait for (8*period);
D_PLUS <= '0';
D_MINUS <= '1';

wait for (8*period);
D_PLUS <= '1';
D_MINUS <= '0';


wait for (8*8*period);
D_PLUS <= '0';
D_MINUS <= '0';
wait for (8*period);
D_PLUS <= '1';
D_MINUS <= '0';
       
       --Case: ERROR - PROBLEM!!!!
       wait;

--$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$





----     RST_N <= '1';
----     R_ENABLE <= '0';
----     D_PLUS <= '1'; --??????????????????  
----     D_MINUS <= '0'; --?????????????????? 
----     wait for period;
----     RST_N <= '0';
----     --wait for 16*period;
----     wait for 8*period;
----     RST_N <= '1';
----------------------------------
----     wait for 8*period;
----     R_ENABLE <='1';
----     ---wait for 8*period;
----     ---R_ENABLE <='0';
----
----     ----wait for 8*period;
----     --D_PLUS <= '0'; --??????????????????  
----     --D_MINUS <= '1'; --?????????????????? 
----     wait for 8*period;
----
------????????????????????????????
------????????????????????????????
----      D_PLUS <= '1';
----      D_MINUS <= '0';
----      wait for (8*period);
----      D_PLUS <= '0';
----      D_MINUS <= '1';
----
------=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+
------=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+
------=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+
----
------=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+
----
------ --=====XM CASE==========
----       wait for (8*period);
----       D_PLUS <= '1';
----       D_MINUS <= '0';
----       wait for (8*period);
----       D_PLUS <= '0';
----       D_MINUS <= '1';
---- 
----       wait for (8*period);
----       D_PLUS <= '1';
----       D_MINUS <= '0';
---- 
----       wait for (8*period);
----       D_PLUS <= '0';
----       D_MINUS <= '1';
---- 
----       wait for (8*period);
----       D_PLUS <= '1';
----       D_MINUS <= '0';
---- 
----       wait for (8*period);
----       D_PLUS <= '0';
----       D_MINUS <= '1';
----       
----       wait for (8*period);
----       D_PLUS <= '0';
----       D_MINUS <= '1';
----
-----------Received the SYNC BIT     
----       -------------------
----       wait for (8*period);
----       D_PLUS <= '0';
----       D_MINUS <= '1';
----       
----       
----       --wait;
---- 
---- --=====Case(iv)====================================================================================
----       wait for (6*8*period); --Isn't this worng? EOP will only occur in (1,2,3,...)*8*period.
---- --=================================================================================================
---- 
----       --wait for (2*8*period);
----       wait for (8*period);
----       D_PLUS <= '0';
----       D_MINUS <= '0';
----
----       wait for (8*period);
----       D_PLUS <= '1';
----       D_MINUS <= '0';
----       
------------------------------------------------------       
------------------------------------------------------
------
------
----wait for (8*period);
----D_PLUS <= '0';
----D_MINUS <= '1';
----
----wait for (8*period);
----D_PLUS <= '1';
----D_MINUS <= '0';
----
----wait for (8*period);
----D_PLUS <= '0';
----D_MINUS <= '1';
----
----wait for (8*period);
----D_PLUS <= '1';
----D_MINUS <= '0';
----
----
----wait for (8*8*period);
----D_PLUS <= '0';
----D_MINUS <= '0';
----wait for (8*period);
----D_PLUS <= '1';
----D_MINUS <= '0';
----
----
----
----       
----       
----       wait;
-- -- --=========================

--=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+
--$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
 --==========Case(iii)==========
--        wait for (8*8*2*period);
--        D_PLUS <= '0';
--        D_MINUS <= '0';
--        wait for (8*period);
--        D_PLUS <= '1';
--        D_MINUS <= '0';
--        wait for (8*period);
--        D_PLUS <= '0';
--        D_MINUS <= '1';
-- 
--        wait for (8*period);
--        D_PLUS <= '1';
--        D_MINUS <= '0';
--        wait for (8*period);
--        D_PLUS <= '0';
--        D_MINUS <= '1';
--        wait;
--==============================
--=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+
--=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+
--=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+























--$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
      --Case(iii) followed by (ii)
      wait for (8*8*2*period);
      D_PLUS <= '0';
      D_MINUS <= '0';
      wait for (8*period);
      D_PLUS <= '1';
      D_MINUS <= '0';
      wait for (8*period);
      D_PLUS <= '0';
      D_MINUS <= '1';
------------------------------------
      wait for (8*period);
      D_PLUS <= '1';
      D_MINUS <= '0';
      wait for (8*period);
      D_PLUS <= '0';
      D_MINUS <= '1';
------------------------------------
      wait for (8*period);
      D_PLUS <= '1';
      D_MINUS <= '0';

      wait for (8*period);
      D_PLUS <= '0';
      D_MINUS <= '1';

      wait for (8*period);
      D_PLUS <= '1';
      D_MINUS <= '0';

      wait for (8*period);
      D_PLUS <= '0';
      D_MINUS <= '1';

      wait for (8*period);
      D_PLUS <= '1';
      D_MINUS <= '0';

------------------------------------
      wait for (8*period);
      wait for (8*period);
      D_PLUS <= '0';
      D_MINUS <= '0';
      wait for (8*period);
      D_PLUS <= '1';
      D_MINUS <= '0';
-----------------------------------
     wait;

 

  end process;
end TEST;